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1 (13) da6180c.000 26 november, 2010 MAS6180C am receiver ic ? single band receiver ic ? high sensitivity ? very low power consumption ? wide supply voltage range ? power down control ? control for agc on ? high selectivity by crystal filter ? fast startup feature description the mas6180 am-receiver chip is a highly sensitive, simple to use am receiver specially intended to rec eive time signals in the frequency range from 40 khz to 100 khz. only a few external components are required fo r time signal receiver. the circuit has preamplifier, wide range automatic gain control, demodulator and outpu t comparator built in. the output signal can be processed directly by an additional digital circuit ry to extract the data from the received signal. the cont rol for agc (automatic gain control) can be used to swi tch agc on or off if necessary. features applications ? single band receiver ic ? highly sensitive am receiver, 0.4 v rms typ. ? wide supply voltage range from 1.5 v to 5.5 v ? very low power consumption ? power down control ? fast startup ? only a few external components necessary ? control for agc on ? wide frequency range from 40 khz to 100 khz ? high selectivity by quartz crystal filter ? differential input ? single band time signal receiver wwvb (usa), jjy (japan), dcf77 (germany), msf (uk), hgb (switzerland) and bpc (china) block diagram agc amplifier power supply/biasing demodulator & comparator rfip rfim vdd vss pdn agc dec out qop qi qom aon vdd vdd this is preliminary information on a new product under development. micro analog systems oy reserves the right to make any changes without notice.
2 (13) da6180c.000 26 november, 2010 mas6180 pad layout vdd qop qom qi agc out dec aon pdn rfip rfim vss 1160 ? m 1320 ? m vss pad bonded first! MAS6180Cx die size = 1160 m x 1320 m; pad size = 80 m x 80 m note: because the substrate of the die is internally conn ected to vss, the die has to be connected to vss or left floating. please make sure that vss is the first pa d to be bonded. pick-and-place and all component as sembly are recommended to be performed in esd protected ar ea. note: coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. pad identification name x-coordinate y-coordinate n ote power supply voltage vdd 126 m 1122 m positive quartz filter output qop 126 m 955 m negative quartz filter output qom 126 m 787 m 1 quartz filter input for crystal qi 126 m 604 m agc capacitor agc 126 m 435 m receiver output out 126 m 258 m 2 demodulator capacitor dec 1034 m 261 m agc on control aon 1034 m 445 m 3 power down pdn 1034 m 613 m 4 positive receiver input rfip 1034 m 802 m 5 negative receiver input rfim 1034 m 980 m 5 power supply ground vss 1034 m 1111 m notes: 1) qom bonding pad is electrically unconnected in m as6180c1 version 2) out = vss when carrier amplitude at maximum; out = vdd when carrier amplitude is reduced (modulated ) - the output is a current source/sink with |i out | > 5 a - at power down the output is pulled to vss (pull do wn switch) 3) aon = vss means agc off (hold current gain level ); aon = vdd means agc on (working) - internal pull-up with current < 1 a which is switched off at power down 4) pdn = vss means receiver on; pdn = vdd means re ceiver off fast start-up is triggered when the receiver is aft er power down (pdn=vdd) controlled to power up (pdn=vss) i.e. at the falling edge of pdn signal. 5) receiver inputs rfip and rfim have both 1.4 m biasing resistors towards vdd
3 (13) da6180c.000 26 november, 2010 6) absolute maximum ratings all voltages with respect to ground parameter symbol conditions min max unit supply voltage v dd -v ss - 0.3 +5.5 v input voltage v in v ss -0.3 v dd +0.3 v esd rating v esd for all pins, human body model (hbm) 2 kv latchup current limit i lut for all pins 100 ma operating temperature t op -40 +85 c storage temperature t st - 55 +150 c stresses beyond those listed may cause permanent da mage to the device. the device may not operate unde r these conditions, but it will not be destroyed. note: in latchup testing the supply voltages are connect ed normally to the tested device. then pulsed test current is fed to each input separately and device current consumption is observ ed. if the device current consumption increases sud denly due to test current pulses and the abnormally high current consumption continu es after test current pulses are cut off then the d evice has gone to latch up. current pulse is turned on for 10 ms and off for 20 ms. electrical characteristics operating conditions: vdd = 5.0v, temperature = 25 c, unless otherwise specified. parameter symbol conditions min typ max unit operating voltage v dd t a = -40c..+85c 1.5 5.0 5.5 v vdd=1.5 v, vin=0.4 vrms vdd=5 v, vin=0.4 vrms 66 68 80 a current consumption i dd vdd=1.5 v, vin=20 mvrms vdd=5 v, vin=20 mvrms 43 45 65 a stand-by current i ddoff see note below. 0.1 a input frequency range f in 40 100 khz minimum input voltage v in min 0.4 1 vrms maximum input voltage v in max 20 mvrms receiver input resistance receiver input capacitance r rfi c rfi differential input, f=77.5 khz 600 1.1 k pf input levels |l in |<0.5 a v il v ih v dd -0.35 0.35 v output current v ol <0.2 v dd ;v oh >0.8 v dd |i out | 5 15 a dcf77 output pulses t 100ms t 200ms 1 vrms v in 20 mvrms, see note below! 95 195 ms msf output pulses t 100ms t 200ms t 500ms 1 vrms v in 20 mvrms, see note below! 120 220 520 ms wwvb output pulses t 200ms t 500ms t 800ms 1 vrms v in 20 mvrms, see note below! 200 500 800 ms jjy60 output pulses t 200ms t 500ms t 800ms 1 vrms v in 20 mvrms, see note below! 210 505 800 ms jjy40 output pulses t 200ms t 500ms t 800ms 1 vrms v in 20 mvrms, see note below ! 200 495 790 ms startup time t start fast start-up, vin=0.4 vrms fast start-up, vin=20 mvrms 1.3 3.5 4 s output delay time t delay 50 100 ms note: stand-by current consumption may increase if v ih and v il differ from vdd and 0 respectively. note: see note 6: time signal software?s pulse width rec ognition limits and table 5 on page 7!
4 (13) da6180c.000 26 november, 2010 typical application receiver output c agc 10 ? f c dec 47 nf note 2 note 1 ferrite antenna note 4 optional control for agc on/hold note 3 power down / fast startup control MAS6180C1 note 5 +5v agc amplifier power supply/biasing demodulator & comparator rfip rfim vdd vss pdn agc dec out qop qi qom aon vdd vdd c vdd 10 ? f r vdd 10 ? figure 1. application circuit of internal compensation capaci tance option version MAS6180C1.
5 (13) da6180c.000 26 november, 2010 typical application (continued) note 1: crystals the crystal as well as ferrite antenna frequencies are chosen according to the time-signal system (tab le 1). more detailed crystal nominal frequency is normally spec ified for certain load capacitance but in mas6180 f ilter circuit the load capacitance is not used. effectively this means that most accurate filter frequency is achiev ed by using about 3 hz higher frequency crystal than the receiv ed time signal frequency. for example in dcf77 appl ication a 77.503 khz crystal resonates at the desired dcf77 7 7.500 khz frequency when the load capacitor is miss ing. table 1. time-signal system frequencies time-signal system location antenna frequency recom mended crystal frequency dcf77 germany 77.5 khz 77.503 khz hgb switzerland 75 khz 75.003 khz msf united kingdom 60 khz 60.003 khz wwvb usa 60 khz 60.003 khz jjy japan 40 khz and 60 khz 40.003 khz and 60.003 k hz bpc china 68.5 khz 68.505 khz the crystal shunt capacitance c 0 should be matched as well as possible with the int ernal shunt capacitance compensation capacitor c c of mas6180. see compensation capacitance options o n table 2. table 2 . compensation capacitance options device c c crystal description MAS6180C1 0.75 pf for low c 0 crystals it should be noted that grounded crystal package ha s reduced shunt capacitance. this value is about 85 % of floating crystal shunt capacitance. for example cry stal with 1 pf floating package shunt capacitance c an have 0.85 pf grounded package shunt capacitance. pcb tra ces of crystal should be kept at minimum to minimiz e additional parasitic capacitance which can cause ca pacitance mismatching. table 3 below presents some crystal manufacturers h aving suitable crystals for time signal receiver ap plication. table 3. crystal manufacturers and crystal types in alphabet ical order for time signal receiver application manufacturer crystal type dimensions web link citizen cfv-206 ? 2.0 x 6.0 http://www.citizen.co.j p/tokuhan/quartz/ epson toyocom c-2-type c-4-type ? 1.5 x 5.0 ? 2.0 x 6.0 http://www.epsontoyocom.co.jp/english/ kds daishinku dt-261 ? 2.0 x 6.0 http://www.kds.inf o/index_en.htm microcrystal ms3v-t1r 1.45 x 1.45 x 6.7 http://www. microcrystal.com/ seiko instruments vtc-120 ? 1.2 x 4.7 http://www.sii-crystal.com
6 (13) da6180c.000 26 november, 2010 typical application (continued) note 2: agc capacitor the agc and dec capacitors must have low leakage cu rrents due to very small signal currents through th e capacitors. the insulation resistance of these capa citors should be at minimum 100 m . also probes with at least few 100 m impedance should be used for voltage probing of the agc and dec pins. electrolytic agc capacitor should have voltage rating at least 25 v for low enough leakage. dec capacitor can be low le akage chip capacitor. it is recommended to connect both agc and dec capac itors to vdd (see application figure 1) although vs s connection is also possible. the vdd connection pro vides better supply noise immunity because signals are referenced to vdd. additionally leakage currents ar e minimized in this connection because in power dow n the agc pin voltage is pulled to vdd (to minimum agc ga in) then corresponding to zero voltage over the agc capacitor. note 3: power down / fast startup control both power down and fast startup are controlled usi ng the pdn pin. the device is in power down (turned off) if pdn = vdd and in power up (turned on) if pdn = vss. fast startup is triggered automatically by the fal ling edge of pdn signal, i.e., controlling device from power down to power up. the vdd must be high before falli ng edge of pdn to guarantee proper operation of fast startup c ircuitry. before power up the device should have be en kept in power down state at least 50ms. this guarantees tha t the agc capacitor voltage has been completely pul led to vdd during power down. the startup time without pro per fast startup control can be over minute but wit h fast startup it is shortened typically to few seconds. note 4: optional control for agc on/hold aon control pin has internal pull up which turns ag c circuit on all the time if aon pin is left unconn ected. optionally aon control can be used to hold and rele ase agc circuit. stepper motor drive of analog cloc k or watch can produce disturbing amount of noise which can shift the input amplifier gain to unoptimal lev el. this can be avoided by controlling agc hold (aon=vss) during stepper motor drive periods and releasing agc (aon=vdd) when motors are not driven. the agc shoul d be in hold only during disturbances and kept on o ther time released since due to leakage the agc voltage can change slowly even when in hold. note 5: ferrite antenna the ferrite antenna converts the transmitted radio wave into a voltage signal. it has an important rol e in determining receiver performance. recommended anten na impedance at resonance is around 100 k . low antenna impedance corresponds to low noise but often also to small signal amplitude. on the other hand high antenna impedance corresponds to high noise bu t also large signal. the optimum performance where signal-to-noise ratio is at maximum is achieved in between. the antenna should have also some selectivity for r ejecting near signal band disturbances. this is det ermined by the antenna quality factor which should be approxim ately 100. much higher quality factor antennas suff er from extensive tuning accuracy requirements and possible tuning drifts by the temperature. antenna impedance r ant can be calculated using equation 1 where f res , l, q ant and c are resonance frequency, coil inductance, antenna quality factor and antenna tuning capacitor respectively. antenna quality fac tor q ant is defined by ratio of resonance frequency f res and antenna bandwidth b (equation 2). c b c f q q l f r res ant ant res ant ? ? = ? ? = ? ? ? = 2 1 2 2 equation 1. b f q res ant = equation 2. table 4 on next page presents some antenna manufact urers for time signal application.
7 (13) da6180c.000 26 november, 2010 typical application (continued) table 4. antenna manufacturers and antenna types in alphabet ical order for time signal application manufacturer antenna type dimensions web link c.e.c coils ap/ar antenna bars http://www.ceccoils .com/cecweb/index .aspx?lang=en hr electronic gmbh 60716 (60 khz) 60708 (77.5 khz) ? 10 x 60 mm http://www.hrelectronic.com/ hitachi metals an-t702sxx an-t702mxx an-t702lxx 19 x 5.5 x 6.3 mm 28 x 5 x 5 mm 50 x 5 x 5 mm http://www.hitachi- metals.co.jp/e/prod/prod06/p06_12.html premo rca-smd-77a (77.5 khz) rca-smd-60a (60 khz) 75 x 15 x 6.3 mm http://www.grupopremo.com/ sumida acl80a (40 khz) ? 10 x 80 mm www.sumida.co.j p/jeita/xja021.pdf note 6: time signal software?s pulse width recognit ion limits the typical output pulse width specifications are p resented in the electrical characteristics section on page 3. due to process variations the typical output pulse widt h can differ from these. additionally the output pu lse widths can vary even more depending on the receiving antenna s ignal strength versus noise and disturbance conditi ons. that is why it is important that the time signal de coding software has appropriate tolerance limits fo r managing the output pulse width variations successfully. the table 5 presents recommended software pulse width tolerance limits for recognizing pulses of different time sig nals. table 5. recommended software pulse width recognition limits for different time signals parameter symbol min max unit dcf77 output pulses t 100ms t 200ms 40 140 130 250 ms msf output pulses t 100ms t 200ms t 500ms 50 170 400 160 300 600 ms wwvb output pulses t 200ms t 500ms t 800ms 100 400 700 300 600 900 ms jjy60 output pulses t 200ms t 500ms t 800ms 100 400 700 300 600 900 ms jjy40 output pulses t 200ms t 500ms t 800ms 100 400 700 300 600 900 ms
8 (13) da6180c.000 26 november, 2010 MAS6180C samples in dil-20 package top marking definitions: yyww = year week xxxxx.x = lot number zz =sample version 1 vdd 2 3 qop 4 qom 5 6 qi 7 agc 8 9 out 10 20 vss 19 18 rfim 17 rfip 16 15 14 pdn 13 aon 12 dec 11 mas6180zz yyww xxxxx.x pin description pin name pin type function note 1 nc vdd 2 p positive power supply 3 nc qop 4 ao positive quartz filter output qom 5 ao negative quartz filter output 1 6 nc 2 qi 7 ai quartz filter input for crystal agc 8 ao agc capacitor 9 nc out 10 do receiver output 3 11 nc dec 12 ao demodulator capacitor aon 13 di agc on control 4 pdn 14 di power down input 5 15 nc 16 nc rfip 17 ai positive receiver input 6 rfim 18 ai negative receiver input 6 19 nc vss 20 g power supply ground a = analog, d = digital, p = power, g = ground, i = input, o = output, nc = not connected notes: 1) qom pin is electrically unconnected in MAS6180C1 version 2) pin 6 between qom and qi must be connected to vs s to eliminate dil package lead frame parasitic capacitances disturbing the crystal filter performa nce. all other nc (not connected) type pins are als o recommended to be connected to vss to minimize nois e coupling. 3) out = vss when carrier amplitude at maximum; out = vdd when carrier amplitude is reduced (modulated ) - the output is a current source/sink with |i out | > 5 a - at power down the output is pulled to vss (pull do wn switch) 4) aon = vss means agc off (hold current gain level ); aon = vdd means agc on (working) - internal pull-up with current < 1 a which is switched off at power down 5) pdn = vss means receiver on; pdn = vdd means re ceiver off - fast start-up is triggered when the receiver is af ter power down (pdn=vdd) controlled to power up (pdn=vss) i.e. at the falling edge of pdn signal. 6) receiver inputs rfip and rfim have both 1.4 m biasing resistors towards vdd
9 (13) da6180c.000 26 november, 2010 pin configuration & top marking for plastic tssop-1 6 package qop vdd qom qi agc out vss rfim rfip pdn aon dec 6180zz yyww top marking definitions: zz = version yyww = year week pin description pin name pin type function note vdd 1 p positive power supply qop 2 ao positive quartz filter output qom 3 ao negative quartz filter output 1 4 nc 2 qi 5 ai quartz filter input for crystal agc 6 ao agc capacitor 7 nc out 8 do receiver output 3 dec 9 ao demodulator capacitor aon 10 di agc on control 4 pdn 11 di power down input 5 12 nc rfip 13 ai positive receiver input 6 14 nc rfim 15 ai negative receiver input 6 vss 16 g power supply ground a = analog, d = digital, p = power, g = ground, i = input, o = output, nc = not connected notes: 1) qom pin is electrically unconnected in MAS6180C1 version 2) pin 4 between qom and qi must be connected to vs s to eliminate tssop package lead frame parasitic capacitances disturbing the crystal filter performa nce. all other nc (not connected) type pins are als o recommended to be connected to vss to minimize nois e coupling. 3) out = vss when carrier amplitude at maximum; out = vdd when carrier amplitude is reduced (modulated ) - the output is a current source/sink with |i out | > 5 a - at power down the output is pulled to vss (pull do wn switch) 4) aon = vss means agc off (hold current gain level ); aon = vdd means agc on (working) - internal pull-up with current < 1 a which is switched off at power down 5) pdn = vss means receiver on; pdn = vdd means re ceiver off - fast start-up is triggered when the receiver is af ter power down (pdn=vdd) controlled to power up (pdn=vss) i.e. at the falling edge of pdn signal. 6) receiver inputs rfip and rfim have both 1.4 m biasing resistors towards vdd
10 (13) da6180c.000 26 november, 2010 package (tssop-16) outlines dimension min max unit a 6.40 bsc mm b 4.30 4.50 mm c 5.00 bsc mm d 0.05 0.15 mm e 1.10 mm f 0.19 0.30 mm g 0.65 bsc mm h 0.18 0.28 mm i 0.09 0.20 mm i1 0.09 0.16 mm j 0.19 0.30 mm j1 0.19 0.25 mm k 0 8 l 0.24 0.26 mm m (the length of a terminal for soldering to a substrate) 0.50 0.75 mm n 1.00 ref mm o 12 p 12 dimensions do not include mold flash, protrusions, or gate burrs. all dimensions are in accordance with jedec standar d mo-153. b a c pin 1 d seating plane e h g f b b detail a l k m n p o detail a i i1 j j1 section b-b
11 (13) da6180c.000 26 november, 2010 soldering information u for pb-free, rohs compliant tssop-16 resistance to soldering heat according to rsh test iec 68-2-58/20 maximum temperature 260 c maximum number of reflow cycles 3 reflow profile thermal profile parameters stated in ipc/jedec j-std-020 should not be exceeded. http://www.jedec.org seating plane co-planarity max 0.08 mm lead finish solder plate 7.62 - 25.4 m, material matte tin embossed tape specifications dimension min max unit a 0 6.50 6.70 mm b 0 5.20 5.40 mm d 0 1.50 +0.10 / -0.00 mm d 1 1.50 mm e 1 1.65 1.85 mm f 1 7.20 7.30 mm k 0 1.20 1.40 mm p 11.90 12.10 mm p 0 4.0 mm p 2 1.95 2.05 mm s 1 0.6 mm t 0.25 0.35 mm w 11.70 12.30 mm p 0 p p 2 a 0 d 1 d 0 a a section a - a e 1 f 1 w tape feed direction b 0 t k 0 s 1 tape feed direction pin 1 designator
12 (13) da6180c.000 26 november, 2010 reel specifications dimension min max unit a 330 mm b 1.5 mm c 12.80 13.50 mm d 20.2 mm n 50 mm w 1 (measured at hub) 12.4 14.4 mm w 2 (measured at hub) 18.4 mm trailer 160 mm leader 390, of which minimum 160 mm of empty carrier tape sealed with cover tape mm weight 1500 g d a b c n w 1 w 2 tape slot for tape start components trailer leader carrier tape cover tape start end 2000 components on each reel reel material: conductive, plastic antistatic or st atic dissipative carrier tape material: conductive cover tape material: static dissipative
13 (13) da6180c.000 26 november, 2010 ordering information product code product description capacitance option MAS6180C1tc00 single band am-receiver ic with differential input ews-tested wafer, diameter 8?, thickness 395 m 5%. c c = 0.75 pf MAS6180C1uc06 single band am-receiver ic with differential input tssop-16, pb-free, rohs compliant, tape & reel c c = 0.75 pf contact micro analog systems oy for other wafer thi ckness options. u the formation of product code an example for MAS6180C1tc00: mas6180 c 1 tc 00 product name design version capacitance option: c c = 0.75 pf package type: tc = 400 m thick ews tested wafer delivery format: 00 = undiced wafer 05 = dies on tray 06 = tape & reel 08 = in tube local distributor micro analog systems oy contacts micro analog systems oy kutomotie 16 fi-00380 helsinki, finland tel. +358 10 835 1100 fax +358 10 835 1109 http://www.mas-oy.com notice micro analog systems oy reserves the right to make changes to the products contained in this data shee t in order to improve the design or performance and to supply the best possible product s. micro analog systems oy assumes no responsibilit y for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specifi ed in this data sheet, and makes no claim that the circuits are free from patent infrin gement. applications for any devices shown in this data sheet are for illustration only and micro analog systems oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.

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